Field of the Invention
The invention relates to a circuit configuration for the bit-parallel outputting of a data word.
The memory cells in a semiconductor memory are usually configured in a matrix-like grid of rows and columns. For reading out the information stored therein, provision is made of signal lines via which bit groups in the form of data words are transferred in parallel. Different logic states xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, which differ in terms of the voltage level, are transferred. The logic stage xe2x80x9c0xe2x80x9d corresponds to a voltage of 0 V, for example, and the logic stage xe2x80x9c1xe2x80x9d corresponds to a voltage of 2.5 V, for example.
Integrated circuits are operated with rising processing speeds and higher transfer frequencies in order to increase the data throughput. The data are transferred to the downstream peripherals via high-speed transfer links. High transfer frequencies, in particular, lead to increased distortion, interference and disturbance of the signals to be transferred and impair the signal quality and detectability.
Depending on the peripherals connected to the signal lines, different load behaviors result at the output drivers of a memory chip and substantially influence the output time behavior of the data to be transferred. The signals are transferred in a delayed manner in the case of a large output load, and, moreover, the signal characteristics, such as the steepness of rising and falling edges, for example, are altered or distorted. The number of signal states that change during the transfer of a data word, such as, for example, the signal state change from a logic xe2x80x9c0xe2x80x9d to a logic xe2x80x9c1xe2x80x9d, and vice versa, influences the signal output characteristics, in particular also the time behavior during the signal outputting. By way of example, in the case of a data word in which all the bits have the logic value xe2x80x9c1xe2x80x9d, the signal states of the data word bits to be transferred in parallel bring about a retarded outputting compared with data words in which the bits have mixed signal states with logic xe2x80x9c1xe2x80x9ds and logic xe2x80x9c0xe2x80x9ds. For the amplification of a signal to be transferred, amplifier stages are connected downstream of the memories and amplify an applied signal by a defined factor corresponding to the specifications.
The operation of one or more amplifier stages in high-frequency circuit environments increasingly requires a very fast changeover of changing signal states, in particular in order to improve the output signal characteristics. Various types of amplifier circuits are used for reading out data of, for example, an integrated semiconductor memory.
For the purpose of reading out a bit of a data signal, an amplifier is connected to a data line on which the signal representing a bit is transferred. In an integrated memory with a matrix-type memory cell array, the memory cells are assigned to word lines and bit lines (or row and column lines). The transferred data are in each case detected and amplified by a sense amplifier. The data are forwarded via a plurality of functional units which set the data read path to downstream amplifier or driver stages, so-called output drivers. Many of the output drivers have complementary field-effect transistors of a p-channel type and an n-channel type that are connected in series. A plurality of identical transistors which represent a further amplifier stage may be connected in parallel with the p-channel and n-channel field-effect transistors.
An input signal applied to an amplifier stage is amplified by a specific factor. Hitherto, only in the production process has it been possible to set and alter the driver strength of an amplifier stage and also the number of effective amplifier stages of a circuit configuration. For a correspondingly required output power of an amplifier stage, the gain factor is determined depending on manufacturing tolerances and component specifications in the manufacturing process. In addition, in the manufacturing process it is possible to alter the number of abovementioned field-effect transistors connected in parallel with the main transistors and hence the number of amplifier stages by connecting or disconnecting interconnect runs. The driver strength is set by the connection or disconnection of field-effect transistors connected in parallel. However, the driver strength can no longer be altered after the conclusion of the manufacturing process. Consequently, the gain factor of an amplifier stage is fixedly predetermined. The amplifier stages found in integrated circuits do not enable requirement-conforming connection or disconnection of amplifier stages in order to adapt signal characteristics and throughput speeds at the transfer points, the so-called pads.
It is accordingly an object of the invention to provide a circuit configuration that is suitable as an amplifier stage, that avoids propagation time delays during the bitwise parallel transfer of a data word, and that improves signal quality.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for outputting bits of a data word in parallel. The configuration includes a plurality of signal lines for providing data signals in parallel. The data signals represent at least two bits of a data word that includes at least two bits. The configuration includes: a plurality of output terminals for providing amplified data signals representing the bits of the data word; and a control device having at least two outputs for outputting a respective control signal. The control device has at least two inputs connected to the signal lines. The control device is for determining signal states of data signals representing bits of two directly successive data words on the plurality of signal lines. The configuration also includes a plurality of driver stages having inputs for obtaining the data signals from the plurality of signal lines. The plurality of driver stages have outputs connected to the plurality of output terminals. The configuration also includes a plurality of additional driver stages, connected in parallel with the inputs and the outputs of the plurality of the driver stages. Each one of the plurality of additional driver stages is connected in parallel with a respective one of the plurality of the driver stages. The control device is for generating a plurality of control signals for enabling or switching off the plurality of additional driver stages. Each one of the plurality of the additional driver stages has an input connected to a respective one of the outputs of the control device for receiving one of the plurality of control signals generated by the control device.
The circuit configuration can advantageously be used for the additional amplification of the data signals to be transferred on the signal lines in that, by using control signals of the upstream control device, the additional driver stages can additionally be connected in parallel with the respective main transistors or first and further driver stages and thus perform an additional amplification of the data signals to be transferred.
The outputting of a data word from a semiconductor memory may be effected, for example, by using data words having a width of 4, 8 or 16 bits. That is to say that the outputting of the data word is effected bitwise in parallel via a corresponding number of signal lines. The data signalsxe2x80x94representing the bits of the data words to be transferredxe2x80x94are fed in parallel via a corresponding number of signal lines to the control device. The control device performs, on each signal line, an evaluation of the signal state changes of the data signals representing the bits of directly successive data words. Depending on the evaluation result, the control device generates a control signal that is fed to the downstream additional driver stages in order to switch the latter on or off. If signal state changes of two data words that are to be transferred directly in succession are present on two signal lines, the control device drives those additional driver stages that are assigned to the signal path for which a signal state change is present within the signal state pairs. By way of example, if signal state changes of two data words that are to be transferred directly in succession are present on three signal lines, the control device drives those additional driver stages which are assigned to those signal paths for which identical signal state changes are present within the signal state pairs. That is to say, either a rising edge followed by a falling edge of a data signal or a falling edge followed by a rising edge of a data signal. If signal state changes of two data words that are to be transferred directly in succession are present on more than three signal lines, the control device drives those additional driver stages that are assigned to the signal path for which a signal state change is present within the signal state pairs.
During the operation of the first and further driver stages, it is now possible to perform the amplification of the data word present in bit-parallel fashion on the signal lines in an adapted manner, depending on the number of state changes of the bits within the signal state pairs of data signals to be transferred, in order to reduce delayed signal outputs. The circuit takes account of the requirement of performing an additional amplification of the signal edges during the transfer of changing signal states on each individual signal line, in order to improve the signal quality.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for the bit-parallel outputting of a data word, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.